In communication systems, data may be optically transmitted through optical fibers. Electro-optical data converters are used for converting electrical data signals into optical signals. Differential non-return to zero (NRZ) formats are used at data rates of about 10 Gbps and beyond. Signal shaping techniques have to be applied for compensating deficiencies and inherent non-idealities of transmission media, as for example frequency dependent losses. In order to reduce power consumption, power supply levels are reduced.
Electro-optical data converters may include a driver and a light emitting semiconductor device as for example a VCSEL (Vertical Cavity Surface Emitting Laser) diode. VCSELs are often used as light emitting semiconductor devices. A VCSEL's circular beam is easily coupled with a fiber. This is mainly due to the characteristic of VCSEL diodes as a surface emission rather than edge emission device and they are known for their excellent power efficiency and durability. Accordingly, VCSEL diodes are widely used in low cost optical transmission systems. However, in high data rate transmission systems, the VCSEL diodes show some drawbacks. For the typical driving circuits, the VCSEL diodes represent a significantly high capacitance and the asymmetric turn on and turn off behavior often results in asymmetric optical eye plots. In order to optimize the bit error rate of the optical transmission link, it is desired to maximize the horizontal and vertical opening of the optical eye plot, i.e. to make the optical eye plot more symmetric. Existing VCSEL drivers therefore introduce output current peaking for steeper optical edges and a threshold adjustment capability in order to correct the eyes crossing point. Both enhancements increase the eye opening, but they fail to render the optical output eye more symmetric. A symmetric optical output eye represents the optimal solution for maximization of vertical and horizontal eye opening thereby minimizing the bit error rate. Theoretical and experimental studies have shown that symmetric optical eyes can be achieved by driving the VCSEL diode with a pre-distorted current signal showing single-sided or asymmetric current peaking. Such a solution is for example described in “A 20 Gb/s VCSEL Driver with Pre-Emphasis and Regulated Output Impedance in 0.13 μm CMOS, by D. Kucharski, Y. Kwark, D. Kuchta et al. This prior art solution superimposes a current peak to the tail current of the output driver, thereby creating an undershoot on its output signal. Both, the width and the height of the undershoot are fixed. The width of the undershoot is limited to the bit width of the input signal. By superimposing the peak current to the driver's tail current the output common mode and the crossing point of the output eye are shifted. Due to its single-sided and fixed peak value implementation, this solution does not allow a flexible adjustment to accommodate different data rates, different VCSEL diode parameters and to compensate the influence of the transmission media and the optical sub assembly.
FIG. 1 shows a circuit diagram of driver circuit for driving a VSCEL diode. An input stage comprises a differential pair of bipolar diodes Q1 and Q2. They are configured to receive differential input signal VIN with their base inputs INp, INn. The input stage further comprises resistor loads RL1, RL2 coupled to respective collectors of transistors Q1, Q2. Furthermore, there is current source coupled to the emitters of both transistors Q1, Q2 defining a tail current I1 through the differential pair. The collectors of transistors Q1, Q2 of the input differential pair provide an output signal VIN2 which is fed to an output stage which also comprises a differential pair of bipolar transistors Q3, Q4. The output stage also comprises resistor loads RL3, RL4 and a current source I2. The output voltage VOUT at the collectors (output nodes OUTn, OUTp) of the differential pair Q3, Q4 may then be used to drive the light VCSEL. The output current IOUT is the difference of the currents I3 and I4 through transistors Q3 and Q4. In a simplified equation, the output current IOUT can be defined as:
                    IOUT        =                  I          ⁢                                          ⁢                      2            ·                          tanh              ⁡                              (                                                      VIN                    ⁢                                                                                  ⁢                    2                                                        2                    ⁢                    VT                                                  )                                                                        (        1        )            where VT is the temperature voltage VT=k T/e with T being the absolute temperature and e the elementary charge. The output voltage can then be determined as:
                    VOUT        =                              RL            ·            IOUT                    =                                    RL              ·              I                        ⁢                                                  ⁢            2            ⁢                          tanh              ⁡                              (                                                      VIN                    ⁢                                                                                  ⁢                    2                                                        2                    ⁢                    VT                                                  )                                                                        (        2        )            
With RL=RL3=RL4. This means that VOUT is a non-linear function of VIN2. However, as long as the input voltage swing of VIN2 exceeds approximately two times VT, the tail current I2 is completely switched from one branch (e.g. Q3) of the differential pair Q3, Q4 to the other side (e.g. Q4). Only for this condition VIN>2 VT, the output voltage VOUT approximates a linear function of I2, i.e. VOUT=RL*I2.
FIG. 2 shows another prior art driving stage. This driving stage differs from the one in FIG. 1 in that an additional differential pair Q5, Q6 is coupled in parallel to the differential pair Q3, Q4. The differential pair Q3, Q4 also receives VIN2 as input voltage from the input stage. The output current IOUT is now superimposed of currents IOUT3,4=IQ3−IQ4 and IOUT5,6=IQ5−IQ6. The result is an overshoot current generated at every edge of signal VIN2. The output voltage VOUT also shows the overshoot. The overshoot height and width may be controlled by filter elements RE5, RE6 and CE as well as the magnitude of current I3. Therefore, the circuit of FIG. 2 can be regarded as a pre-emphasis output driver, which may be used for compensating losses of transmission lines. However, since this superimposed output driver operates in limiting mode (i.e. VIN2>2 VT), the output signals show for example undesired common mode ripple VOUT,CM=(VOUTp+VOUTn)/2 at the output terminals OUTp, OUTn, where VOUTp is the voltage at node OUTp and VOUTn the voltage at node OUTn. This is due to a high frequency ripple at the emitter nodes VE2, VE3. This ripple converts into a common mode voltage ripple at the output nodes caused by the finite input impedances of the current sources I2 and I3, which are indicated with ZI2, ZI3. The common-mode ripple causes increased EMI which may adversely affect system requirements. Furthermore, the capacitive loading of the output terminals is increased as two differential pairs of transistors are coupled to the input stage. This aspect decreased the achievable bandwidth and therefore the maximum data rate.